FPGA-Based Realization of UART

By aid of embedded technology, the Multi-channel full duplex serial port is realized by means of FPGA. This design has added an 8-buffer-cell FIFO in front of transmitting terminal and receiving terminal in order to achieve rate adaptation between the internal module clock and UART. Besides, the serial port baud rate can be set to cater for needs of different communication baud．The experimental results are subjected to verification on the hardware FPGA Cyclone III platform of the Altera Company, which finds the design fully UART compatible.